Hayes, Ari B; Hua, Fei; Huang, Jin; Chen, Yanhao; Zhang, Eddy Z Decoding CUDA Binary Conference Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2019), IEEE Press, Washington, DC, USA, 2019, ISBN: 9781728114361. Abstract | BibTeX | Tags: Code generation, Code translation and transformation, CUDA, GPU, Instruction set architecture (ISA)
2019
@conference{10.5555/3314872.3314900,
title = {Decoding CUDA Binary},
author = {Ari B Hayes and Fei Hua and Jin Huang and Yanhao Chen and Eddy Z Zhang},
isbn = {9781728114361},
year = {2019},
date = {2019-01-01},
booktitle = {Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2019)},
pages = {229–241},
publisher = {IEEE Press},
address = {Washington, DC, USA},
abstract = {NVIDIA’s software does not offer translation of assembly code to binary for their GPUs, since the specifications are closed-source. This work fills that gap. We develop a systematic method of decoding the Instruction Set Architectures (ISAs) of NVIDIA’s GPUs, and generating assemblers for different generations of GPUs. Our framework enables cross-architecture binary analysis and transformation. Making the ISA accessible in this manner opens up a world of opportunities for developers and researchers, enabling numerous optimizations and explorations that are unachievable at the source-code level. Our infrastructure has already benefited and been adopted in important applications including performance tuning, binary instrumentation, resource allocation, and memory protection.},
keywords = {Code generation, Code translation and transformation, CUDA, GPU, Instruction set architecture (ISA)},
pubstate = {published},
tppubtype = {conference}
}
NVIDIA’s software does not offer translation of assembly code to binary for their GPUs, since the specifications are closed-source. This work fills that gap. We develop a systematic method of decoding the Instruction Set Architectures (ISAs) of NVIDIA’s GPUs, and generating assemblers for different generations of GPUs. Our framework enables cross-architecture binary analysis and transformation. Making the ISA accessible in this manner opens up a world of opportunities for developers and researchers, enabling numerous optimizations and explorations that are unachievable at the source-code level. Our infrastructure has already benefited and been adopted in important applications including performance tuning, binary instrumentation, resource allocation, and memory protection.
